1. Field of the Invention
The present invention relates to hybrid circuits and devices fabricated from superconductor materials combined with semiconductor devices that can be operated at low temperatures. More particularly, the present invention relates to improving read access times for random access MOS memories by adding Josephson Junction superconductors to make a hybrid circuit that improves the read access speed and reduces the power consumption.
2. Description of the Related Art
The discovery of superconductors whose critical operating temperatures are above liquid nitrogen temperature prompted increased interest in hybrid superconducting-semiconducting electronic circuit applications. The possibilities for using superconducting devices for interconnecting conventional semiconductor circuits and devices have been studied. See, for example, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Kroger, et al., proceedings of the IEEE, Vol. 77, No. 8, August 1989; T. van Duzer, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Cryogenics, Vol. 28, pp. 527-31 (1988); H. Kroger, "Josephson Devices Coupled by Semiconductor Links," IEEE Trans. Electron Devices, Vol. ED-27, pp. 2016-126 (1980).
Superconductors are devices having no resistance to current flow. Superconducting Josephson Junctions have the unique property of no voltage drop, i.e., no resistance to current flow below a certain critical threshold current, I.sub.c. FIG. 1 illustrates a plan view of a schematic representation of a Josephson Junction. Referring now to FIGS. 1 and 2, similar elements of FIG. 1 also in FIG. 2 will be represented with a suffix "a." In FIGS. 1 and 2, superconducting base electrode 20 is deposited on an integrated circuit substrate 32. Insulator 24 is deposited over base electrode 20. A hole 26 is formed into insulator 24 of about 2 micrometers in diameter and through various surface treatments, well known in the art, a very thin insulating layer called a "thin barrier layer" covers the bottom of the hole 26. The superconducting top electrode 22 is deposited over insulator 24 and into hole 26. Electrodes 20 and 22 may be any type of superconductor, such as, for example, niobium ("Nb") or niobium nitride ("NbN"). Electrodes 20 and 22 may be comprised of the same or different superconducting material. The device comprising hole 26, thin insulating barrier 34 and electrodes 20 and 22 is called a Josephson Tunnel Junction ("JJ"). Ohmic contacts 28 and 30 are attached to superconducting electrodes 20 and 22, respectively, for connection to non-superconducting circuits such as integrated circuit MOS transistors.
The JJ described above has the unique property of having no voltage drop between superconducting electrodes 20 and 22 as current flows through the tunnel junction formed at barrier 34. The size of hole 26, however is critical in that the diameter and subsequent area of the hole 26 gives the JJ its ability to maintain zero voltage potential across the tunnel junction until a certain critical current, I.sub.c, is reached. Referring now to FIG. 3, a current-voltage characteristic curve (I-V) is illustrated for a typical JJ. The JJ current-voltage characteristic curve illustrated in FIG. 3 has a maximum critical current (I.sub.c ") 50 up to which no voltage drop appears across the JJ. When current through the JJ exceeds I.sub.c 50, then the zero voltage drop condition ceases to exist and a voltage drop ("V.sub.gap ") 54 results across the junction 34. Thus, a gap voltage 54 appears between electrodes 20 and 22. The gap voltage 54, V.sub.gap, illustrated in FIG. 3 remains as a potential voltage difference between the electrodes 20 and 22 until the JJ current is reduced to a minimum current 58 wherein the JJ returns to the superconducting state, i.e., no voltage drop across the junction 34. The JJ device is useful for the high speed at which it may be switched from a superconducting to non-superconducting state, typically on the order of 10 picoseconds. The JJ device is bi-directional, i.e., current may flow in either direction, and the resulting current-voltage characteristic curve is a negative mirror image about the x-y axis. Thus, the negative critical current I.sub.c 52 when exceeded causes a negative gap voltage 56 to appear across the JJ junction 34 and the negative V.sub.gap 56 will remain until current flow through the JJ is reduced to a minimum current 60, causing the JJ to return to the superconducting condition. Gap voltage 54 for niobium is typically 2.55 millivolts. Typical operating conditions for a JJ would be for about 100 microamperes of current to flow, thus, biasing the JJ to a point just below the critical current, I.sub.c. If current greater than I.sub.c flows through the JJ, then the JJ will switch into the voltage gap non-superconducting mode and remain there so long as the biasing current continues through the JJ electrodes 20 and 22. The JJ may be reset from the V.sub.gap mode to the superconducting mode by removing current flow from the junction. After resetting the JJ by removing the current flow therefrom, the JJ will remain in the superconducting mode until current flow through it once again exceeds the critical current 50.
Referring now to FIGS. 4a and 4b, a JJ is illustrated with a third element called a control loop 70 above electrode 22b and junction hole 26b. FIG. 4b is a cross-sectional view of the FIG. 4a JJ. Elements of FIGS. 1 and 2 also referred to in FIGS. 4a and 4b will have a suffix "b" after the element number. When a current passes through control loop 70, the JJ critical current I.sub.J value is altered. Current flowing between electrode 20 and 22 through tunnel junction 34 creates a magnetic field that may be altered by a magnetic field created from current flow through control loop 70. The resulting magnetic field generated from the current flow in control loop 70 modulates the magnetic field surrounding the thin barrier 34 and alters the value of the critical current I.sub.c necessary to switch from the superconducting to the V.sub.gap mode.
Referring now to FIGS. 5a and 5b, the relationships between critical current, I.sub.c, and control loop current, I.sub.n, are illustrated graphically. FIG. 5a illustrates the I.sub.c versus I.sub.n curve for a JJ having a very small hole 26. FIG. 5b illustrates the I.sub.c versus I.sub.n curve for a JJ having an elongated hole 26 that is large in the direction of the I.sub.J current. The JJ is normally biased at bias current 82 and is in the superconducting mode. A region 84 exists under curve 80 wherein the JJ remains superconducting, however, if the currents I.sub.J or I.sub.n are changed to bias the JJ at a point above the curve 80, then the JJ will switch to the V.sub.gap region 86 and no longer be superconducting. For example, if the loop current, I.sub.n, is increased, while bias current 82 remains constant, to the point where the critical current, curve 80, is less than the bias current 82, then the JJ will switch from the superconducting to the V.sub.gap mode. For the elongated hole JJ, the I.sub.c versus the I.sub.n curve 80a is not symmetric about I.sub.n =0. This non-symmetry may be used to advantage to detect the polarity of the I.sub.n current (direction of current flow).
In summary, control loop current, I.sub.n, may be used to alter the value of the critical current required to switch the JJ from its superconducting to its V.sub.gap mode or, in the alternative, the control loop current may be used to prevent the JJ from switching from the superconducting mode. Thus, the JJ has either no voltage drop in its superconducting mode or a very small voltage drop when in the V.sub.gap mode. Changing from superconducting to V.sub.gap mode is current dependent and happens very quickly. The usefulness of the JJ will become more apparent in the detailed description of the present invention.
Referring now to FIG. 6a, a random access memory cell and supporting select logic is illustrated schematically. A memory cell 106 may be either of static or dynamic configuration. A memory cell is generally any one-bit binary circuit with a voltage input and output. For example, the circuit may be as simple as a pair of capacitors as in FIG. 6b, or as complex as a four transistor latch as illustrated in FIG. 6c. Memory cell 106 is representative of many memory cells of like structure comprising an integrated circuit random access memory ("RAM"). A RAM integrated circuit is organized in rows and columns wherein a particular memory cell is designated by the intersection of a selected row and column. Information is read from memory cell 106 by enabling MOS transistors 104 and 138 by means of a voltage signal on word line 102. When the word line 102 activates transistors 104 and 138, the data contents of memory cell 106 connects to bit lines 97 and 127. Next, a read access signal is placed on line 108 which enables MOS transistors 110 and 128, connecting the bit lines 97 and 127, containing the memory cell 106 data, to differential amplifier data receiver 130 inputs 132 and 134, respectively.
During a write operation, data to be written appears on outputs 94 and 124. The complement of the data is connected to input 92 and inverted by inverter 90, likewise, the data is connected to input 122 and becomes the complement on output 124. MOS transistors 96 and 126 turn on when a write access signal on line 98 goes high. The write data information connects to bit lines 97 and 127 through the transistors 96 and 126, forcing the memory cell 106 contents to conform to the write data.
The aforementioned memory read and write operations all require relatively large voltage swings of from 2 to 5 volts to operate the MOS transistor circuits. Electronic integrated circuit elements have capacitance that must be charged or discharged to the appropriate logic voltage levels in order to operate the circuit. In most cases, the higher the capacitance and the higher the voltage swing that is required to operate an electronic circuit, the longer it takes to switch from one voltage level to another voltage level. The inherent voltage charging requirement, often referred to as a circuit's RC time constant, limits the speed in which a random access memory may be written to or read from. Various methods have been introduced to reduce the length of the RC charging time constant by reducing the amount of capacitance inherent in the integrated circuit and/or reducing the amount of voltage change necessary. In addition, reducing the amount of resistance inherent in the switching circuits reduces the RC time constant, however, this may increase power dissipation of the integrated circuit and may not be practical in implementing large scale random access memory.